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RT9605B 1 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively general description the RT9605B is a high frequency, triple-channel synchronous-rectified buck mosfet driver specifically designed to drive six power n-mosfets. the part is promoted to pair with richtek's multiphase buck pwm controller family for high-density power supply implementation. the output drivers of RT9605B can efficiently switch power mosfets at frequency 300khz typically. operating in higher frequency should consider the thermal dissipation carefully. each driver of RT9605B is capable to drive a 3nf load in 30/40ns rising/falling time with little propagation delay from input transition to the gate of the power mosfet. the device implements bootstrapping on the upper gate with only an external capacitor and a diode required. this reduces circuit complexity and allows the use of higher performance, cost effective n-mosfets. all drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. the RT9605B also detects the fault condition during initial start-up prior to the multi-phase pwm controller takes control. as a result, the input supply will latch into the shutdown state. the RT9605B comes to a small footprint package with vqfn-24l 4x4 package. features z z z z z drive six n-mosfets for 3-phase buck pwm control z z z z z adaptive shoot-through protection z z z z z support high switching frequency z z z z z fast output rising/falling time z z z z z propagation delay 40ns z z z z z tri-state input for bridge shutdown z z z z z upper mosfet direct short protection z small 24-lead vqfn package z z z z z rohs compliant and 100% lead (pb)-free applications z cpu core voltage supplies on motherboard z high frequency low profile dc/dc converters z high current low voltage dc/dc converters triple-channel synchronous-rectified buck mosfet driver ordering information marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. pin configurations (top view) vqfn-24l 4x4 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ugate1 gnd gnd lgate3 pvcc3 boot2 ugate2 gnd pwm2 pwm1 nc boot1 24 18 6 5 4 3 2 1 13 14 15 16 17 9 8 7 101112 23 22 21 20 19 pwm3 vdd boot3 ugate3 phase3 gnd phase1 lgate1 pvcc1 pvcc2 lgate2 phase2 gnd package type qv : vqfn-24l 4x4 (v-type) lead plating system p : pb free g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) RT9605B
RT9605B 2 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively typical application circuit functional pin description ugate1 (pin 1), ugate2 (pin 17), ugate3 (pin 10) upper gate drive output. should be connected to the upper mosfet gate. boot1 (pin 2), boot2 (pin 16), boot3 (pin 9) floating bootstrap supply pin for the upper gate drive. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. nc (pin 3) no connected. pwm1 (pin 4), pwm2 (pin 5), pwm3 (pin 7) pwm input control signal. connect this pin to the pwm output of the controller. if the pwm signal enters and remains within the shutdown window, are both ugate and lgate are drived low, disabling the output mosfets. gnd (pin 6, 12, 13, 18 ) chip power ground. vdd (pin 8) supply input. connect to +5v stand-by power. place a bypass capacitor between this pin and gnd. phase1 (pin 24), phase2 (pin 19), phase3 (pin 11) upper driver return. should be connected to the common node of upper and lower mosfets. the phase voltage is monitored for adaptive shoot-through protection. lgate1 (pin 23), lgate2 (pin 20), lgate3 (pin 14) lower gate drive output. should be connected to the lower mosfet gate. pvcc1 (pin 22), pvcc2 (pin 21), pvcc3 (pin 15) supply input. connect to +12v supply. place a bypass capacitor between this pin and pgnd. exposed pad exposed pad should be soldered to pcb board and connected to gnd. phase3 phase2 phase1 pi dacq dacfb pgood pwm3 pwm2 isp3 isp2 fb comp vdd pwm1 rt dvd icommon isp1 vid0 vid2 vid3 vid4 vid1 vid5 3.3v 12v v core 5v sb 9 3 5 47 2 812 11 10 14 15 13 16 1 6 gnd 15k 10nf 33pf 3k 4.7f optional optional optional 1f 1f 1f 430 3k 16k 27k 10k 1.8k 110k 56k 27k 13k 6.8k 3.3k r r r rt8800 5.1k boot2 pwm3 pwm2 pwm1 boot1 lgate3 pvcc3 phase3 ugate3 boot3 ugate2 pvcc2 phase2 lgate2 nc ugate1 pvcc1 phase1 lgate1 vdd 12v 5v sb phase1 v in phase2 v core phase3 1242223 9 10 11 15 14 3 8 20 21 19 17 16 7 5 4 2 gnd 12v 12v 12v v in 1f 1000f 1h 0 1f 1f 0 10 1f 3.3nf 2.2 1f 0 1f 0 3.3f 2.2 0.5h 0.5h 0.5h 1f 0 3.3nf 2.2 0 1f 10f x 4 1000f x 12 RT9605B 1500f x 4 v in optional optional r droop r icommon1 r icommon2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 c1 c2 c3 c4 c8 c9 c10 to c13 c5 c6 c7 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 to c35 c36 to c39 d1 d2 d3 q1 q2 q3 q4 q5 q6 q7 q8 q9 l1 l2 l3
RT9605B 3 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively function block diagram timing diagram control logic boot1 ugate1 phase1 pvcc1 lgate1 gnd boot2 ugate2 phase2 pvcc2 lgate2 gnd boot3 ugate3 phase3 pvcc3 lgate3 gnd pwm1 pwm2 pwm3 short-through protection short-through protection short-through protection vdd vdd vdd pwm ugate lgate t rugate t pdugate t fugate t rlgate t flgate t pdlgate 90% 10% 90% 10% 90% 10% 90% 10%
RT9605B 4 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively absolute maximum ratings (note 1) z driver supply voltage, pvcc -------------- -------------------------------------------------------- ? 0.3v to 15v z core supply voltage, vdd ------------------------------------------------------------------------- ? 0.3v to 7v z boot to phase ------------------------------------------------------------------------------------- ? 0.3v to 15v z phase to gnd dc -------------------------------------------------------------------------------------------------------- ? 5v to 15v < 20ns --------------------------------------------------------------------------------------------------- ? 10v to 30v z lgate dc -------------------------------------------------------------------------------------------------------- (gnd ? 0.3v) to (v pvcc + 0.3v) < 20ns --------------------------------------------------------------------------------------------------- ? 2v to (v pvcc + 0.3v) z ugate dc -------------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) < 20ns --------------------------------------------------------------------------------------------------- (v phase ? 2v) to (v boot + 0.3v) z pwm input v oltage ---------------------------------------------------------------------------------- (gnd ? 0.3v) to 7v z package thermal resistance (note 2) vqfn-24l 4x4, ja ---------------------------------------------------------------------------------- 67 c/w z junction temperature -------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------------------------------------------------- 260 c z storage temperature range ---------------------------- ------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------- 2kv mm (ma chine mode) --------------------------------------------------------------------------------- 150v electrical characteristics recommended operating conditions (note 4) z driver supply voltage, pvcc -------------- -------------------------------------------------------- 12v 10% z core supply voltage, vdd ------------------------------------------------------------------------- 5v 10% z junction temperature range ---------------------------- ------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------- ------------------------------------------- ? 40 c to 85 c (recommended operating conditions, t a = 25 c unless otherwise specified) parameter symbol test conditions min typ max unit vdd supply current operation current i vdd frequency = 250khz -- -- 10 ma power on reset pvcc por threshold v pvcc rising 7.2 8 8.8 v pvcc hysteresis -- 1.1 -- v vdd threshold v dd rising 3.7 4 4.3 v pwm input v pwm _ in = 0v 500 600 700 input current i pwm v pwm _ in = 5v 200 350 500 a floating voltage v pwmfl 1.4 1.8 2.2 v to be continued
RT9605B 5 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit v pw mr th pwm_in rising 2.7 3.1 3.5 v pw m thre sho ld v pwmfth pwm_in falling 0.8 1 1.3 v output ugate rise time t rugat e pv cc = 12v, 3nf load -- 80 -- ns ugate fall time t fugate pv cc = 12v, 3nf load -- 40 -- ns lgate rise time t rlgat e pv cc = 12v, 3nf load -- 40 -- ns lgate fall time t flgate pv cc = 12v, 3nf load -- 25 -- ns ugate turn-off propagation delay t pdugate pv cc = 12v, 3nf load -- 30 -- ns lgate turn-off propagation delay t pdlgate pv cc = 12v, 3nf load -- 25 -- ns shutdown window 0.8 -- 3.5 v
RT9605B 6 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively typical operating characteristics v in = 12v, unless otherwise specified. dead time time (50ns/div) phase 2, falling v out = 1.4v, i out = 30a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 1, falling v out = 1.4v, i out = 0a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 1, rising v out = 1.4v, i out = 0a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 1, falling v out = 1.4v, i out = 30a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 1, rising v out = 1.4v, i out = 30a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 2, falling v out = 1.4v, i out = 0a lgate (5v/div) ugate (5v/div) phase (5v/div)
RT9605B 7 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively dead time time (50ns/div) phase 3, rising v out = 1.4v, i out = 0a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 3, falling v out = 1.4v, i out = 30a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 3, falling v out = 1.4v, i out = 0a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 2, rising v out = 1.4v, i out = 30a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 2, rising v out = 1.4v, i out = 0a lgate (5v/div) ugate (5v/div) phase (5v/div) dead time time (50ns/div) phase 3, rising v out = 1.4v, i out = 30a lgate (5v/div) ugate (5v/div) phase (5v/div)
RT9605B 8 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively power on time (2.5ms/div) v out = 1.4v, i out = 90a v in (10v/div) ugate (20v/div) lgate (10v/div) v out (2v/div) power on time (2.5ms/div) v out = 1.4v, i out = 0a v in (10v/div) ugate (20v/div) lgate (10v/div) v out (2v/div) power off time (25ms/div) v out = 1.4v, i out = 90a v in (10v/div) ugate (20v/div) lgate (10v/div) v out (2v/div) power off time (25ms/div) v out = 1.4v, i out = 0a v in (10v/div) ugate (20v/div) lgate (10v/div) v out (2v/div) efficiency vs. output curreent 76% 78% 80% 82% 84% 86% 88% 90% 0 102030405060708090100 output curreent (a) efficiency (%) v in = 12v, f = 300khz v out = 1.45v 90 88 86 84 82 80 78 76
RT9605B 9 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively application information the RT9605B is designed to drive three sets of both high side and low side n-mosfet through externally input pwm control signal. it has power-on protection function which held ugate and lgate low before pv cc rising across the threshold voltage. after the initialization, the pwm signal takes the control. the rising pwm signal first forces the lgate turns low then ugate is allowed to go high just after a non-overlapping time to avoid shoot- through. the falling of pwm signal first forces ugate to go low. when ugate and phase reach a predetermined low level, lgate is allowed to turn high. the non- overlapping function is also presented between ugate and lgate signal transient. the pwm signal is acted as " high " if above the rising threshold and acted as " low " if below the falling threshold. any signal level remaining within the shutdown window is considered as " tri-state " , the output drivers are disabled and both mosfet gates are pulled and held low. if the pwm signal floating, the pin will be kept at 2.1v by the internal divider and provide the pwm controller with a recognizable level. the RT9605B typically operates at frequency of 200khz to 300khz. it shall be noted that to place a 1n4148 or schottky diode between the pvcc and boot pin as shown in the typical application circuit. driving power mosfets the dc input impedance of the power mosfet is extremely high. when v gs at 12v, the gate draws the current only few nano-amperes. thus once the gate has been driven up to " on " level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large current to source and sink the gate rapidly. it also needs to switch drain current on and off with high speed. the required gate drive currents are calculated as follows. in figure 1, the current i g1 and i g2 are required to move the gate up to 12v. the operation consists of charging c gd and c gs . c gs1 and c gs2 are the capacitances from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs is referred as "c iss " which is the input capacitance. c gd1 and c gd2 are the capacitances from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as " c rss " the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are showed below : figure 1. equivalent circuit and associated waveforms 12v t t v g2 v g1 v phase +12v (1) (2) r2 gs2 g2 gs2 gs2 r1 gs1 g1 gs1 gs1 t 12 c dt dv c i t 12 c dt dv c i = = = = l d 2 s 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 c gs1 c gd1 i gd1 i gs1 i g1 d 2 v out s 1 v in d 1 d 1 gnd g 1
RT9605B 10 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively before driving the gate of the high side mosfet up to 12v (or 5v), the low side mosfet has to be off; and the high side mosfet is turned off before the low side is turned on. from figure 1, the body diode " d 2 " had been turned on before high side mosfets turned on. it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v g1 = v g2 = 12v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain from equation. (3) and (4) the total current required from the gate driving source is by a similar calculation, we can also get the sink current required from the turned off mosfet. select the bootstrap capacitor figure 2 shows part of the bootstrap circuit of RT9605B. the v cb (the voltage difference between boot and phase pins provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c b has to be selected properly. it is determined by following constraints. figure 2. part of bootstrap circuit of RT9605B (4) (3) (5) (6) (7) (8) (9) (10) before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 12v, the required current is v in c b v cb + - boot ugate phase lgate gnd 1n4148 in practice, a low value capacitor c b will lead the over- charging that could damage the ic. therefore to minimize the risk of overcharging and reducing the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low-esr capacitor should be used to provide good local de-coupling. here, to adopt either a ceramic or tantalum capacitor is suitable. power dissipation for not exceeding the maximum allowable power dissipation to drive the ic beyond the maximum recommended operating junction temperature of 125 c, it is necessary to calculate power dissipation appro- priately. this dissipation is a function of switching frequency and total gate charge of the selected mosfet. figure 3 shows the power dissipation test circuit. c l and c u are the ugate and lgate load capacitors, respectively. the bootstrap capacitor value is 1 f. r1 gd1 gd1 gd1 t 12v c dt dv c i = = r2 in gd2 gd2 gd2 t 12 v c dt dv c i = = (a) 88 . 0 10 0 3 12 10 2200 i (a) 428 . 1 10 14 12 10 1660 i 9 - 12 - 9 - -12 gs2 gs1 = = = = (a) 4 . 0 10 0 3 ) 12 12 ( 10 00 5 i (a) 326 . 0 10 14 12 10 80 3 i 9 - 12 - 9 - -12 gd2 gd1 = + = = = (a) 28 . 1 ) 4 . 0 88 . 0 ( i i i (a) 745 . 1 ) 326 . 0 428 . 1 ( i i i gd2 gs2 g2 gd1 gs1 g1 = + = + = = + = + =
RT9605B 11 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively over voltage protection function at power on an unique feature of the RT9605B is the addition of over voltage protection in the event of upper mosfet direct shorted before power on. the RT9605B detects the fault condition during initial start-up, the internal power on ovp sense circuitry will rapidly drive the low side mosfet on before the multi-phase pwm controller takes control. figure 5 shows the measured waveforms with the high side mosfet directly shorted to 12v. please note that the +12v trigger point to RT9605B is at 3v, and the clamped level on phase pin is at about 2.4v. obviously since the phase pin voltage increases during initial start-up, the v core increases correspondingly, but it would quickly drop-off following the voltage in lgate and +12v. layout consideration figure 6 shows the schematic circuit of a two-phase synchronous buck converter to implement the either phase of RT9605B. the converter operates at v in 12v. figure 4 shows the power dissipation of the RT9605B as a function of frequency and load capacitance. the value of the c u and c l are the same and the frequency is varied from 100khz to 1mhz. the operating junction temperature can be calculated from the power dissipation curves (figure 4). assume vdd = 12v, operating frequency is 200khz and the c u =c l =1nf which emulate the input capacitances of the high side and low side power mosfets. from figure 4, the power dissipation is 100mw. for RT9605B, the package thermal resistance ja is 67 c/w, the operating junction temperature is calculated as : t j = (67 c/w x 100mw) + 25 c = 31.7 c (11) where the ambient temperature is 25 c. the method to improve the thermal transfer is to increase the pc board copper area around the RT9605B firstly. then, adding a ground pad under ic to transfer the heat to the peripheral of the board. figure 3. test circuit ( one phase is shown) figure 5. waveform s at high side mosfet shorted +12v phase x lgate x v core figure 4. power di ssipation vs. frequency power dissipation vs. frequency 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 frequency (khz) power dissipation (mw) c u =c l =3nf c u =c l =1nf c u =c l =2nf figure 6. sync. buck converter circuit vdd pwm x gnd boot x ugate x phase x lgate x RT9605B 1f c l 3nf 20 c u 3nf 2n7002 2n7002 12v 12v 1f pwm 1n4148 c bootx 10 boot x ugate x phase x lgate x pvcc x pwm x RT9605B gnd 1 f phb83n03lt phb95n03lt 2 h 1 f 1000 f 1.2 h 12v 1500 f l1 c1 l2 c3 q2 q1 c2 cb d1 pwm v in v core + + 10 1 f 12v r1 c4
RT9605B 12 ds9605b-03 march 2011 www.richtek.com all brandname or trademark belong to their owner respectively when layout the pc board, it should be very careful. the power-circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the junction of q1, q2, l2 should be very close. next, the trace from ugate, and lgate to the gates of mosfet should also be short to decrease the noise of the driver output signals. the bypass capacitor c4 should be connected to gnd directly. furthermore, the bootstrap capacitors (c b ) should always be placed as close to the pins of the ic as possible. the trace from phase to the common node of the two mosfets should be kept wide since it usually carries large current.
RT9605B 13 ds9605b-03 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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